View C165_372330.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Microcomputer Components
16-Bit CMOS Single-Chip Microcontroller
C165
Data Sheet 09.94
C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary C165 16-Bit Microcontroller
q q q q q q q q q q q q q q q q q q q q q q q q
C165
q q q
High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20-MHz CPU Clock 500 ns Multiplication (16 x 16 bits), 1 s Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Up to 16 MBytes Linear Address Space for Code and Data 2 KBytes On-Chip RAM 4 KBytes On-Chip ROM (RM types only) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/Data Buses Five Programmable Chip-Select Signals Hold- and Hold-Acknowledge Bus Arbitration Support 1024 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 50 ns Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) Programmable Watchdog Timer Up to 77 General Purpose I/O Lines Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 100-Pin MQFP Package (EIAJ) 100-Pin TQFP Package (Thin QFP) - Attention
09.94 Data Sheet Addendum
The C165 is offered in two different packages: P-MQFP-100: rectangular package P-TQFP-100: square package. For the pin configurations please refer to page 3 (P-MQFP-100) and page 8 (P-TQFP-100) of the 09.94 C165 Data Sheet. Please note that the table "Pin Definition and Functions" on pages 9 through 12 lists the pin numbers for the MQFP package only. The pin numbers for the TQFP package are different and should be taken from the pin configuration on page 3. Semiconductor Group 1 09.94
C165
Introduction The C165 is a new derivative of the Siemens SAB 80C166 family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced IO-capabilities.
C165
Figure 1 Logic Symbol Ordering Information Type SAB-C165-RM Ordering Code Q67121-D... Package P-MQFP-100-2 Function 16-bit microcontroller with 2 KByte RAM and 4 KByte ROM Temperature range 0 to +70 C 16-bit microcontroller with 2 KByte RAM Temperature range 0 to +70 C 16-bit microcontroller with 2 KByte RAM Temperature range -40 to +85 C
SAB-C165-LM
Q67121-C862
P-MQFP-100-2
SAF-C165-LM
Q67121-C923
P-MQFP-100-2
Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product after verification of the respective ROM code.
Semiconductor Group
2
C165
Ordering Information Type SAB-C165-RF Ordering Code Q67121-D... Package P-TQFP-100-3 Function 16-bit microcontroller with 2 KByte RAM and 4 KByte ROM Temperature range 0 to +70 C 16-bit microcontroller with 2 KByte RAM Temperature range 0 to +70 C
SAB-C165-LF
Q67121-C941
P-TQFP-100-3
Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Pin Configuration TQFP Package (top view)
C165
Figure 2
Semiconductor Group
3
C165
Pin Configuration MQFP Package (top view)
C165
Figure 3
Semiconductor Group
4
C165
Pin Definitions and Functions Symbol P5.10 - P5.15 Pin No. 100 1-5 100 1 2 3 4 5 7 8 Input (I) Output (O) I I I I I I I I I O Function Port 5 is a 6-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as timer inputs: P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input P5.12 T6IN GPT2 Timer T6 Count Input P5.13 T5IN GPT2 Timer T5 Count Input P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The following Port 3 pins also serve for alternate functions: P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 TxD0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12 BHE Ext. Memory High Byte Enable Signal, WRH Ext. Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock)
XTAL1 XTAL2
P3.0 - P3.13, P3.15
10 - 23, 24
I/O I/O I/O
11 12 13 14 15 16 17 18 19 20 21 22 23 24
O I O I I I I I/O I/O O I/O O O I/O O
Semiconductor Group
5
C165
Pin Definitions and Functions (cont'd) Symbol P4.0 - P4.7 Pin No. 25 - 28, 31 - 34 Input (I) Output (O) I/O Function Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line ... ... ... P4.7 A23 Most Significant Segment Addr. Line External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the C165 to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. The C165 must have this pin tied to `0'.
25 ... 34 RD WR/ WRL 35 36
O ... O O O
READY
37
I
ALE
38
O
EA
39
I
Semiconductor Group
6
C165
Pin Definitions and Functions (cont'd) Symbol PORT0: P0L.0 - P0L.7, P0H.0 P0H.7 Pin No. 43 - 50 53 - 60 Input (I) Output (O) I/O Function PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0 - P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15 PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the C165. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C165 to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally.
PORT1: P1L.0 - P1L.7, P1H.0 P1H.7
I/O 61 68 69 - 70, 73 - 78
RSTIN
81
I
RSTOUT 82
O
NMI
83
I
Semiconductor Group
7
C165
Pin Definitions and Functions (cont'd) Symbol P6.0 - P6.7 Pin No. 84 91 Input (I) Output (O) I/O Function Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/ pull or open drain drivers. The following Port 6 pins also serve for alternate functions: P6.0 CS0 Chip Select 0 Output ... ... ... P6.4 CS4 Chip Select 4 Output P6.5 HOLD External Master Hold Request Input P6.6 HLDA Hold Acknowledge Output P6.7 BREQ Bus Request Output Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/ pull or open drain drivers. The following Port 2 pins also serve for alternate functions: P2.8 EX0IN Fast External Interrupt 0 Input ... ... ... P2.15 EX7IN Fast External Interrupt 7 Input Flash programming voltage. This pin accepts the programming voltage for flash versions of the C165. Note: This pin is not connected (NC) on non-flash versions. Digital Supply Voltage: + 5 V during normal operation and idle mode. 2.5 V during power down mode Digital Ground.
84 ... 88 89 90 91 P2.8 - P2.15 92 99
O ... O I O O I/O
92 ... 99
I ... I -
VPP
42
VCC
9, 30, 40, 51, 71, 80 6, 29, 41, 52, 72, 79
-
VSS
-
Semiconductor Group
8
C165
Functional Description The architecture of the C165 combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C165. Note: All time specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section).
Figure 4 Block Diagram
Semiconductor Group
9
C165
Memory Organization The memory space of the C165 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The C165 is prepared to incorporate on-chip mask-programmable ROM for code or constant data. Currently no ROM is integrated. 2 KBytes of on-chip RAM are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C165 family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller. External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: - 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed - 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed - 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed - 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory TriState Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories. In addition, different address ranges may be accessed with different bus characteristics. Up to 5 external CS signals can be generated in order to save external glue logic. Access to very slow memories is supported via a particular `Ready' function. A HOLD/HLDA protocol is available for bus arbitration. For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.
Semiconductor Group
10
C165
Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C165's instructions can be executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called `Jump Cache', allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 5 CPU Block Diagram
Semiconductor Group
11
C165
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C165 instruction set which includes the following instruction classes: - - - - - - - - - - - - Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
Semiconductor Group
12
C165
Interrupt System With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the C165 is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C165 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C165 has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible C165 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Note: Four nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit. Also the three listed Software Nodes can be used for this purpose.
Semiconductor Group
13
C165
Source of Interrupt or PEC Service Request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error X-Peripheral Node 0 X-Peripheral Node 1 X-Peripheral Node 2 X-Peripheral Node 3 Software Node Software Node Software Node
Request Flag CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR T2IR T3IR T4IR T5IR T6IR CRIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR XP0IR XP1IR XP2IR XP3IR CC29IR CC30IR CC31IR
Enable Flag CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE T2IE T3IE T4IE T5IE T6IE CRIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE XP0IE XP1IE XP2IE XP3IE CC29IE CC30IE CC31IE
Interrupt Vector CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT T2INT T3INT T4INT T5INT T6INT CRINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT XP0INT XP1INT XP2INT XP3INT CC29INT CC30INT CC31INT
Vector Location 00'0060H 00'0064H 00'0068H 00'006CH 00'0070H 00'0074H 00'0078H 00'007CH 00'0088H 00'008CH 00'0090H 00'0094H 00'0098H 00'009CH 00'00A8H 00'011CH 00'00ACH 00'00B0H 00'00B4H 00'00B8H 00'00BCH 00'0100H 00'0104H 00'0108H 00'010CH 00'0110H 00'0114H 00'0118H
Trap Number 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 22H 23H 24H 25H 26H 27H 2AH 47H 2BH 2CH 2DH 2EH 2FH 40H 41H 42H 43H 44H 45H 46H
Semiconductor Group
14
C165
The C165 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during runtime: Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction NMI STKOF STKUF UNDOPC PRTFLT ILLOPA ILLINA ILLBUS Trap Flag Trap Vector RESET RESET RESET Vector Location 00'0000H 00'0000H 00'0000H Trap Number 00H 00H 00H 02H 04H 06H 0AH 0AH 0AH 0AH 0AH Trap Priority III III III II II II I I I I I
NMITRAP 00'0008H STOTRAP 00'0010H STUTRAP 00'0018H BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028H 00'0028H 00'0028H 00'0028H 00'0028H
[2CH - 3CH] [0BH - 0FH] Any [00'0000H - 00'01FCH] in steps of 4H Any [00H - 7FH] Current CPU Priority
Semiconductor Group
15
C165
General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400 ns (@ 20-MHz CPU clock). The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e. g. position tracking. Timers T3 and T4 have output toggle latches (TxOTL) which change their state on each timer overflow/underflow. The state of these latches may be output on port pins (TxOUT) e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead.
Semiconductor Group
16
C165
Figure 6 Block Diagram of GPT1
Semiconductor Group
17
C165
Figure 7 Block Diagram of GPT2
Parallel Ports The C165 provides up to 77 I/O lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for timer control signals. All port lines that are not used for these alternate functions may be used as general purpose I/O lines.
Semiconductor Group
18
C165
Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). They are upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family and support full-duplex asynchronous communication up to 625 KBaud and half-duplex synchronous communication up to 5 Mbaud (2.5 Mbaud on the ASC0) @ 20-MHz system clock. Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 s and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz).
Semiconductor Group
19
C165
Instruction Set Summary The table below lists the instructions of the C165 in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "C16x Family Instruction Set Manual". This document also provides a detailed description of each instruction.
Instruction Set Summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2
Semiconductor Group
20
C165
Instruction Set Summary (cont'd) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 2/4 2/4 2/4 4 4 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2
Semiconductor Group
21
C165
Special Function Registers Overview The following table lists all SFRs which are implemented in the C165 in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Special Function Registers Overview Name ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 Physical 8-Bit Description Address Address FE18H FE1AH FE1CH FE1EH 0CH 0DH 0EH 0FH 86H 8AH 8BH 8CH 8DH 25H C4H C5H C6H C7H C8H C9H CAH CBH Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register EX0IN Interrupt Control Register EX1IN Interrupt Control Register EX2IN Interrupt Control Register EX3IN Interrupt Control Register EX4IN Interrupt Control Register EX5IN Interrupt Control Register EX6IN Interrupt Control Register EX7IN Interrupt Control Register Software Node Interrupt Control Register Software Node Interrupt Control Register Software Node Interrupt Control Register CPU Context Pointer Register Reset Value 0000H 0000H 0000H 0000H 0XX0H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H FC00H
BUSCON0 b FF0CH BUSCON1 b FF14H BUSCON2 b FF16H BUSCON3 b FF18H BUSCON4 b FF1AH CAPREL CC8IC CC9IC CC10IC CC11IC CC12IC CC13IC CC14IC CC15IC CC29IC CC30IC CC31IC CP FE4AH b FF88H b FF8AH b FF8CH b FF8EH b FF90H b FF92H b FF94H b FF96H
b F184H E C2H b F18CH E C6H b F194H E CAH FE10H 08H
Semiconductor Group
22
C165
Special Function Registers Overview (cont'd) Name CRIC CSP DP0L DP0H DP1L DP1H DP2 DP3 DP4 DP6 DPP0 DPP1 DPP2 DPP3 EXICON MDC MDH MDL ODP2 ODP3 ODP6 ONES P0L P0H P1L P1H P2 P3 P4 Physical 8-Bit Description Address Address b FF6AH FE08H B5H 04H GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (read only) P0L Direction Control Register P0H Direction Control Register P1L Direction Control Register P1H Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Register (10 bits) CPU Data Page Pointer 2 Register (10 bits) CPU Data Page Pointer 3 Register (10 bits) External Interrupt Control Register CPU Multiply Divide Control Register CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Constant Value 1's Register (read only) Port 0 Low Register (Lower half of PORT0) Port 0 High Register (Upper half of PORT0) Port 1 Low Register (Lower half of PORT1) Port 1 High Register (Upper half of PORT1) Port 2 Register Port 3 Register Port 4 Register (8 bits) Reset Value 0000H 0000H 00H 00H 00H 00H 0000H 0000H 00H 00H 0000H 0001H 0002H 0003H 0000H 0000H 0000H 0000H 0000H 0000H 00H FFFFH 00H 00H 00H 00H 0000H 0000H 00H
b F100H E 80H b F102H E 81H b F104H E 82H b F106H E 83H b FFC2H b FFC6H b FFCAH b FFCEH FE00H FE02H FE04H FE06H E1H E3H E5H E7H 00H 01H 02H 03H
b F1C0H E E0H b FF0EH FE0CH FE0EH 87H 06H 07H
b F1C2H E E1H b F1C6H E E3H b F1CEH E E7H FF1EH b FF00H b FF02H b FF04H b FF06H b FFC0H b FFC4H b FFC8H 8FH 80H 81H 82H 83H E0H E2H E4H
Semiconductor Group
23
C165
Special Function Registers Overview (cont'd) Name P5 P6 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PSW RP0H S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSCBR Physical 8-Bit Description Address Address b FFA2H b FFCCH FEC0H FEC2H FEC4H FEC6H FEC8H FECAH FECCH FECEH b FF10H D1H E6H 60H 61H 62H 63H 64H 65H 66H 67H 88H Port 5 Register (read only) Port 6 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register CPU Program Status Word Reset Value XXXXH 00H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
b F108H E 84H FEB4H b FFB0H b FF70H FEB2H b FF6EH 5AH D8H B8H 59H B7H
System Startup Configuration Register (Rd. only) XXH Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register 0000H 0000H 0000H XXH 0000H
b F19CH E CEH FEB0H b FF6CH FE12H 58H B6H 09H
Serial Channel 0 Transmit Buffer Interrupt Control 0000H Register Serial Channel 0 Transmit Buffer Register (write only) Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baudrate Register SSC Control Register SSC Error Interrupt Control Register 00H 0000H FC00H 0000H 0000H 0000H
F0B4H E 5AH D9H BBH
SSCCON b FFB2H SSCEIC b FF76H
Semiconductor Group
24
C165
Special Function Registers Overview (cont'd) Name SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC TFR WDT WDTCON XP0IC XP1IC XP2IC Physical 8-Bit Description Address Address F0B2H E 59H b FF74H BAH SSC Receive Buffer (read only) SSC Receive Interrupt Control Register SSC Transmit Buffer (write only) SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register X-Peripheral 0 Interrupt Control Register X-Peripheral 1 Interrupt Control Register X-Peripheral 2 Interrupt Control Register Reset Value XXXXH 0000H 0000H 0000H FA00H FC00H 0xx0H*) 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
F0B0H E 58H b FF72H FE14H FE16H b FF12H FE40H b FF40H b FF60H FE42H b FF42H b FF62H FE44H b FF44H b FF64H FE46H b FF46H b FF66H FE48H b FF48H b FF68H b FFACH FEAEH FFAEH B9H 0AH 0BH 89H 20H A0H B0H 21H A1H B1H 22H A2H B2H 23H A3H B3H 24H A4H B4H D6H 57H D7H
b F186H E C3H b F18EH E C7H b F196H E CBH
Semiconductor Group
25
C165
Special Function Registers Overview (cont'd) Name XP3IC ZEROS Physical 8-Bit Description Address Address b F19EH E CFH b FF1CH 8EH X-Peripheral 3 Interrupt Control Register Constant Value 0's Register (read only) Reset Value 0000H 0000H
*) The system configuration is selected during reset. Note: The Interrupt Control Registers XPnIC are prepared to control interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.
Semiconductor Group
26
C165
Absolute Maximum Ratings Ambient temperature under bias (TA): SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF ..................................... 0 to + 70 C SAF-C165-LM............................................................................................................ - 40 to + 85 C Storage temperature (TST) ....................................................................................... - 65 to + 150 C Voltage on VCC pins with respect to ground (VSS) ...................................................... -0.5 to + 6.5 V Voltage on any pin with respect to ground (VSS) .................................................- 0.5 to VCC + 0.5 V Input current on any pin during overload condition.................................................. - 10 to + 10 mA Absolute sum of all input currents during overload condition ..............................................|100 mA| Power dissipation..................................................................................................................... 1.5 W Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined by the Absolute Maximum Ratings.
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C165 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C165 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C165.
DC Characteristics
VCC = 5 V 10 %; TA = 0 to +70 C TA = -40 to +85 C
Parameter Input low voltage
VSS = 0 V;
fCPU = 20 MHz; Reset active for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF for SAF-C165-LM Symbol min. Limit Values max. 0.2 VCC - 0.1 V V V V - - - - Unit Test Condition
VIL VIH
SR - 0.5 SR 0.2 VCC + 0.9
Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN Input high voltage XTAL1
VCC + 0.5 VCC + 0.5 VCC + 0.5
VIH1 SR 0.6 VCC VIH2 SR 0.7 VCC
27
Semiconductor Group
C165
Parameter
Symbol min.
Limit Values max. 0.45
Unit V
Test Condition
Output low voltage VOL CC - (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs)
IOL = 2.4 mA
VOL1 CC -
0.45 -
V V
IOL1 = 1.6 mA IOH = - 500 A IOH = - 2.4 mA IOH = - 250 A IOH = - 1.6 mA
0 V < VIN < VCC 0 V < VIN < VCC -
VOH CC 0.9 VCC Output high voltage 2.4 (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT)
Output high voltage (all other outputs)
1)
VOH1 CC 0.9 VCC
2.4
- 200 500 150 -40 - 40 - -40 - -10 - 20 10 10 + 4 * fCPU 2+ 1.2 * fCPU 100
V V nA nA k A A A A A A A A A pF mA mA A
Input leakage current (Port 5) Input leakage current (all other) RSTIN pullup resistor Read/Write inactive current Read/Write active current ALE inactive current ALE active current
4) 4) 4) 4) 4)
IOZ1 CC - IOZ2 CC - RRST CC 50 IRWH IRWL IALEL IALEH IP6H IP6L
4) 2) 3) 2) 3) 2) 3) 2) 3)
- -500 - 500 - -500 - -100
VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max VIN = VIHmin VIN = VILmax
0 V < VIN < VCC
Port 6 inactive current Port 6 active current
4)
PORT0 configuration current XTAL1 input current Pin capacitance (digital inputs/outputs) Power supply current Idle mode supply current
5)
IP0H IP0L IIL
CC -
CIO CC - ICC IID IPD
- - -
f = 1 MHz TA = 25 C
RSTIN = VIL2 fCPU in [MHz] 6) RSTIN = VIH1 fCPU in [MHz] 6)
Power-down mode supply current
VCC = 5.5 V 7)
Semiconductor Group
28
C165
Notes
1)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. Not 100% tested, guaranteed by design characterization. The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VCCmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VCC - 0.1 V to VCC, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
2) 3) 4)
5) 6)
7)
Figure 8 Supply/Idle Current as a Function of Operating Frequency
Semiconductor Group
29
C165
Testing Waveforms
AC inputs during testing are driven at 2.4 V for a logic `1' and 0.4 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. Figure 9 Input Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA). Figure 10 Float Waveforms
Semiconductor Group
30
C165
AC Characteristics External Clock Drive XTAL1 VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF TA = -40 to +85 C for SAF-C165-LM Parameter Symbol Max. CPU Clock = 20 MHz min. Oscillator period High time Low time Rise time Fall time TCL SR 25 max. 25 - - 5 5 25 6 6 - - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. 500 - - 5 5 ns ns ns ns ns Unit
t1 t2 t3 t4
SR 6 SR 6 SR - SR -
Figure 11 External Clock Drive XTAL1
Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol Values
tA tC tF
TCL * 2TCL * (15 - ) 2TCL * (1 - )
Semiconductor Group
31
C165
AC Characteristics (cont'd) Multiplexed Bus VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF TA = -40 to +85 C for SAF-C165-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR max. - - - - - 5 30 - - 30 + tC 55 + tC 55 + tA + tC 70 + 2tA + tC - 35 + tF - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TCL - 10 + tA - TCL - 15 + tA - TCL - 10 + tA - TCL - 10 + tA - -10 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - 2TCL - 15 + tC - 5 TCL + 5 - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 15 + tF - Unit
t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t22
CC 15 + tA CC 10 + tA CC 15 + tA CC 15 + tA CC -10 + tA CC - CC - CC 40 + tC CC 65 + tC SR - SR - SR - SR - SR 0 SR - SR 35 + tC
Semiconductor Group
32
C165
Parameter
Symbol
Max. CPU Clock = 20 MHz min. max. - - - 10 - tA 55 + tC + 2tA - - - 0 25 25 + tC 50 + tC - - - - 30 + tF - -
Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 2TCL - 15 + tF 2TCL - 15 + tF 2TCL - 15 + tF -5 - tA - 3TCL - 15 + tF TCL - 5 + tA -5 + tA - - - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF max. - - - 10 - tA 3TCL - 20 + tC + 2tA - - - 0 TCL 2TCL - 25 + tC 3TCL - 25 + tC - - - - 2TCL - 20 + tF - -
Unit
Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS
t23 t25 t27 t38 t39 t40 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t54 t56
CC 35 + tF CC 35 + tF CC 35 + tF CC -5 - tA SR - CC 60 + tF CC 20 + tA CC -5 + tA CC - CC - SR - SR - CC 40 + tC CC 65 + tC CC 35 + tC SR 0 SR - CC 30 + tF CC 30 + tF
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Semiconductor Group
33
C165
t5
ALE
t16
t25
t38
CSx
t39
t40
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS
t7
t54 t19 t18
Address
Data In
t8
RD
t10 t14 t44 t12 t46 t48 t51 t52
t42
RdCSx
Write Cycle BUS Address
t23
Data Out
t8
WR, WRL, WRH
t10
t56 t22 t12 t50 t48
t42
WrCSx
t44
Figure 12-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE
Semiconductor Group
34
C165
t5
ALE
t16 t38 t39
t25
t40
CSx
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS Address
t7
t54 t19 t18
Data In
t8
RD
t10 t14 t44 t12 t46 t48 t51 t52
t42
RdCSx
Write Cycle BUS Address Data Out
t23
t8
WR, WRL, WRH
t10
t56 t22 t12 t50 t48
t42
WrCSx
t44
Figure 12-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE
Semiconductor Group
35
C165
t5
ALE
t16
t25
t38
CSx
t39
t40
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS
t7
t54 t19 t18
Address
Data In
t9
RD
t11
t15 t13 t51 t52
t43
RdCSx
t45
t47 t49
Write Cycle BUS Address
t23
Data Out
t9
WR, WRL, WRH
t56 t11 t22 t13 t45 t50 t49
t43
WrCSx
Figure 12-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE
Semiconductor Group
36
C165
t5
ALE
t16 t38 t39
t25
t40
CSx
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS Address
t7
t54 t19 t18
Data In
t9
RD
t11
t15 t13 t51 t52
t43
RdCSx
t45
t47 t49
Write Cycle BUS Address Data Out
t23
t56 t9
WR, WRL, WRH
t11 t13
t22
t43
WrCSx
t45 t49
t50
Figure 12-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE
Semiconductor Group
37
C165
AC Characteristics (cont'd) Demultiplexed Bus VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF TA = -40 to +85 C for SAF-C165-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay) Data float after RD rising edge (no RW-delay) Data valid to WR Data hold after WR ALE rising edge after RD, WR max. - - - - - - 30 + tC 55 + tC 55 + tA + tC 70 + 2tA + tC - 35 + tF 15 + tF - - - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TCL - 10 + tA - TCL - 15 + tA - TCL - 10 + tA -10 + tA 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - - 2TCL - 15 + tC -10 + tF - - - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 15 + tF TCL - 10 + tF - Unit
t5 t6 t8 t9 t12 t13 t14 t15 t16 t17 t18 t20 t21 t22 t24 t26
CC 15 + tA CC 10 + tA CC 15 + tA CC -10 + tA CC 40 + tC CC 65 + tC SR - SR - SR - SR - SR 0 SR - SR - CC 35 + tC CC 15 + tF CC -10 + tF
TCL - 10 + tF - -
Semiconductor Group
38
C165
Parameter
Symbol
Max. CPU Clock = 20 MHz min. max. - 10 - tA 55 + tC + 2tA - - - 25 + tC 50 + tC - - - - 30 + tF 5 + tF - -
Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 0 + tF -5 - tA - TCL - 15 + tF TCL - 5 + tA -5 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 - - -5 + tF TCL - 15 + tF max. - 10 - tA 3TCL - 20 + tC + 2tA - - - 2TCL - 25 + tC 3TCL - 25 + tC - - - - 2TCL - 20 + tF TCL - 20 + tF - -
Unit
Address hold after RD, WR ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS
t28 t38 t39 t41 t42 t43 t46 t47 t48 t49 t50 t51 t53 t68 t55 t57
CC 0 + tF CC -5 - tA SR - CC 10 + tF CC 20 + tA CC -5 + tA SR - SR - CC 40 + tC CC 65 + tC CC 35 + tC SR 0 SR - SR - CC -5 + tF CC 10 + tF
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Semiconductor Group
39
C165
t5
ALE
t16
t26
t38
CSx
t39
t41
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t20 t18
Data In
t8
RD
t14 t12
t51 t53
t42
RdCSx
t46 t48
Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH
t24
Data Out
t57 t8 t12 t42 t50 t48 t22
WrCSx
Figure 13-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE
Semiconductor Group
40
C165
t5
ALE
t16 t38 t39
t26
t41
CSx
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t20 t18
Data In
t8
RD
t14 t12 t51 t53
t42
RdCSx
t46 t48
Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH
t24
Data Out
t57 t8 t12 t42 t50 t48 t22
WrCSx
Figure 13-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE
Semiconductor Group
41
C165
t5
ALE
t16
t26
t38
CSx
t39
t41
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t21 t18
Data In
t9
RD
t15 t43 t13 t47 t49 t51 t68
RdCSx
Write Cycle BUS (D15-D8) D7-D0
t24
Data Out
t9
WR, WRL, WRH
t57 t22 t13 t50 t49
t43
WrCSx
Figure 13-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE
Semiconductor Group
42
C165
t5
ALE
t16 t38 t39
t26
t41
CSx
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t21 t18
Data In
t9
RD
t15 t13 t51 t68
t43
RdCSx
t47 t49
Write Cycle BUS (D15-D8) D7-D0
t24
Data Out
t57 t9 t22 t13 t43 t50 t49
WR, WRL, WRH
WrCSx
Figure 13-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE
Semiconductor Group
43
C165
AC Characteristics (cont'd) CLKOUT and READY VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF TA = -40 to +85 C for SAF-C165-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF Parameter Symbol Max. CPU Clock = 20 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) max. 50 - - 5 5 10 + tA - - - - - 0 + 2tA + tF
2)
Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 2TCL TCL - 5 TCL - 10 - - 0 + tA 10 0 2TCL + 15 15 0 0 max. 2TCL - - 5 5 10 + tA - - - - - TCL - 25 + 2tA + tF
2)
Unit
t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60
CC 50 CC 20 CC 15 CC - CC - CC 0 + tA SR 10 SR 0 SR 65 SR 15 SR 0 SR 0
ns ns ns ns ns ns ns ns ns ns ns ns
Notes
1) 2)
These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA refer to the next following bus cycle.
Semiconductor Group
44
C165
Running cycle 1)
READY waitstate
MUX/Tristate 6)
CLKOUT
t32 t30 t34
t33 t31 t29
7)
ALE
Command RD, WR
2)
t35
Sync READY
3)
t36
t35
3)
t36
t58
Async READY
3)
t59
t58
3) 5)
t59
t60
4)
t37
see 6)
Figure 14 CLKOUT and READY
Notes
1) 2) 3)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). The leading edge of the respective command depends on RW-delay. READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. The next external bus cycle may start here.
4)
5)
6)
7)
Semiconductor Group
45
C165
AC Characteristics (cont'd) External Bus Arbitration VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF TA = -40 to +85 C for SAF-C165-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF Parameter Symbol Max. CPU Clock = 20 MHz min. HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive max. - 20 20 20 25 20 25 20 - - - -5 - -5 Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. - 20 20 20 25 20 25 ns ns ns ns ns ns ns Unit
t61 t62 t63 t64 t65 t66 t67
SR 20 CC - CC - CC - CC -5 CC - CC -5
Semiconductor Group
46
C165
CLKOUT
t61
HOLD
t63
HLDA 1)
t62
BREQ
2)
t64
CSx (On P6.x)
3)
t66
Other Signals
1)
Figure 15 External Bus Arbitration, Releasing the Bus
Notes
1) 2) 3)
The C165 will complete the currently running bus cycle before granting bus access. This is the first possibility for BREQ to get active. The CS outputs will be resistive high (pullup) after t64.
Semiconductor Group
47
C165
CLKOUT
2)
t61
HOLD
t62
HLDA
t62
BREQ
t62
1)
t63
t65
CSx (On P6.x)
t67
Other Signals Figure 16 External Bus Arbitration, (Regaining the Bus)
Notes
1)
This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the C165 requesting the bus. The next C165 driven bus cycle may start here.
2)
Semiconductor Group
48

▲Up To Search▲

Price & Availability of C165

	To Download C165 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .